//  Copyright (c) 2010 by Dolphin Technology
//  All rights reserved.
//
//  Copyright Notification
//  No part may be reproduced except as authorized by written permission.
// 
//% @file   dti_shftreg.v
//% @par    Company:
//%             Dolphin Technology 
//% @par    Project:
//%             [projectname]
//% @par    Author:
//%             N. Huy Bui
//% @par    Date: July 9, 2012
//%
//% @brief
//%             parameterized shift-register with parallel load capability
//$Id$

module dti_shftreg #(parameter LENGTH = 5) (
  input 	    clk,
  input 	    load_n,
  input 	    shift_n,
  input 	    s_in,
  input     [LENGTH-1:0] p_in,

  output reg [LENGTH-1:0] p_out);

reg 	  [LENGTH-1:0] p_next; 			//next-state register

//sequential block for updating register state
always @ (posedge clk)
  p_out <= p_next;

//combinational block for calculating next-state logic
always @ (load_n, shift_n, s_in, p_in, p_out)
begin
  if (!load_n)
    p_next = p_in;
  else if (!shift_n)
    p_next = {p_out [LENGTH-2:0], s_in};
  else
    p_next = p_out;
end
endmodule // dti_shftreg
